Image filtering is indispensable for images having low signal to noise ratio obtained in signal processing systems such as image processing systems.
Currently there are mainly two types of filtering methods. The first type of methods use programmable devices such as FPGA, CPLD and the like, and design filters specific to different application scenarios. Such methods provide some level of real time capability, but cannot achieve a high dominant frequency or have diversified functions due to inherent weakness of the programmable devices. As an example, the patent document (application No. 200310105132) discusses how to implement two-dimensional (2D) filtering using CPLD and single chip microcomputer. This method is based on a 5*5 filtering template, and can be executed in real time. However, when the size of the filtering template is changes, the overall structure has to be redesigned. This method is not flexible or modular. Further, the operating frequency 10 M is low.
The second type of methods use specific DSP or ASIC chips. An image is stored in the form of data array in a memory, and the chips filter the image by processing the data array in the memory. Such methods incur heavy access overhead and are inefficient in filtering operation, because conventional signal processors require repeated loading of data to be filtered.
In the scope of the second type of methods, the present disclosure provide an optimized parallel filtering method and designs a structure for filtering operation by using vector operational components according to the method.